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Microcomputer:Important Notices

"TX49/H3 Core Product Specification Update" is updated.

May,2007

Product Types
64-bit RISC microprocessor: TX49 Family
  • TX4961XBG-240
  • TX4962XBG-120
Overview
  1. When the transmitter sends break signal in the middle of sending data, only the first framing error is detected, and a break signal can't be detected.
    The break signal is detected normally, when break signal is synchronized with start bit (The received data is low continuously right after the start bit recognition). (ERT-TX49H3-001)
  2. When a bus error occurs in a certain DMAC channel, there are cases where "all 0" is repeatedly written to an address (DMSARn) in all channels (including the channel where the error occurred) that should be read. At this time, the address value (DMSARn) and Count Register value (DMCNTRn) do not change and writing to the same address continues until the CPU stops DMA transfer (sets DMCCRn.XFACT to 0). (ERT-TX49H3-003)
  3. When a Bus error exception (DBE) occurs during a data Read cycle generated by a preceding load instruction and an exception with a higher priority than the Bus error exception (DBE) occurs in a subsequently executed instruction, the exception of the subsequent instruction is processed first and Bus error exceptions (DBE) are no longer detected. (ERT-TX49H3-006)
  4. If an instruction that works on the TLB is executed in TLB-mapped address space, the target instruction of a branch or jump might not be executed correctly. (ERT-TX49H3-007)
  5. If an SC or SCD instruction is followed by a load or cache instruction or if a register modified by an SC or SCD instruction is referenced by the next instruction, then the result of the latter instruction might be different from what is expected. (ERT-TX49H3-008)
  6. The TX49 core might not be able to return to User mode from Debug mode during PC tracing using an EJTAG ICE. (ERT-TX49H3-009)
  7. When an unimplemented FPU instruction is executed, operation of the following instruction might not be guaranteed. (ERT-TX49H3-010)
  8. When store/load instructions are sequentially executed, an unnecessary write-back might occur. (ERT-TX49H3-011)
  9. An mfc0 instruction immediately before a TLB exception caused by an instruction fetch might read incorrect data from a register under a special condition. (ERT-TX49H3-012)
  10. The EJTAG ICE should not execute the CFC0 and CTC0 instructions while an external bus master using the GREQ/GGNT or GHPGREQ/GHPGGNT signals owns the G-Bus for ET concurrency operations. Otherwise, the GBSTART signal is asserted improperly. (ERT-TX49H3-015)
  11. Wrong data written to and read from CAN registers or TX49 Data Bus Error (DBE) Exceptions may occur when CAN addresses are accessed by TX49 directly after a write access to one of the following modules:
    Graphics Display Controller (GDC), Frame Grabber (FG), Graphics Accelerator (GA), NAND-Flash Controller (NANDFC), Interrupt Controller (INTC), Extended Serial Expansion Interface (ESEI), Chip Configuration Register (CCR), Media Local Bus Interface (MLB), and External DDR Memory which has special conditions.
    Write accesses performed by other Bus-Masters (DMA, MLB) to the above mentioned modules are not causing a problem. (ERT-TX49H3-016)
Details

"TX49/H3 Core Product Specification Update"

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