"TX49/L4 Core Product Specification Update" is released.
May,2007
- Product Types
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- 64-bit RISC microprocessor: TX49 Family
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- TX49/L4 Core
- TX4964FG-120
- Overview
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- When the transmitter sends break signal in the middle of sending data, only the first framing error is detected, and a break signal can't be detected.
The break signal is detected normally, when break signal is synchronized with start bit (The received data is low continuously right after the start bit recognition). (ERT-TX49L4-001) - When a bus error occurs in a certain DMAC channel, there are cases where "all 0" is repeatedly written to an address (DM0SARn) in all channels (including the channel where the error occurred) that should be read. At this time, the address value (DM0SARn) and Count Register value (DM0CNTRn) do not change and writing to the same address continues until the CPU stops DMA transfer (sets DM0CCRn.XFACT to 0). (ERT-TX49L4-002)
- When a Bus error exception (DBE) occurs during a data Read cycle generated by a preceding load instruction and an exception with a higher priority than the Bus error exception (DBE) occurs in a subsequently executed instruction, the exception of the subsequent instruction is processed first and Bus error exceptions (DBE) are no longer detected. (ERT-TX49L4-003)
- If an instruction that works on the TLB is executed in TLB-mapped address space, the target instruction of a branch or jump might not be executed correctly. (ERT-TX49L4-004)
- The TX49 core might not be able to return to User mode from Debug mode during PC tracing using an EJTAG ICE. (ERT-TX49L4-005)
- The EJTAG ICE should not execute the CFC0 and CTC0 instructions while an external bus master using the GREQ/GGNT or GHPGREQ/GHPGGNT signals owns the G-Bus for ET concurrency operations. Otherwise, the GBSTART signal is asserted improperly. (ERT-TX49L4-006)
- When the transmitter sends break signal in the middle of sending data, only the first framing error is detected, and a break signal can't be detected.
